The invention relates to an ESD protection structure. In particular, it relates to a protection structure using a MOS device.
CMOS devices have traditionally been used for ESD protection. A typical CMOS device is illustrated in FIG. 1 in which the polygate can be used as a self-aligned mask to produce a small drain-source spacing between the drain 14 and the source 16. The gate 10 which is of the order of 0.18 xcexcm in the case of 0.18 xcexcm technology allows a drain-source spacing of the order of 0.1 xcexcm to be achieved. However the snapback triggering voltage is typically 2 to 3 times higher than the operating power supply voltage. Traditionally, in order to reduce the triggering voltage, gate potential has been appropriately controlled. However, this produces only about a 20% reduction.
A schematic representation of the structure of FIG. 1 is shown in FIG. 2 which defines the gap 12 in the p-well 18. The gap 12 extends between a lightly doped drain region 20 of the drain 14, and a lightly doped source region 22 of the source 16. As is shown in the electric field versus x-dimension graph in FIG. 2B, the electric field gradually increases from the source to the drain. Furthermore, the curves 24 become ever steeper as the voltage across the drain and source is increased. The effect of this is that hole concentration at the drain gradually increases with increasing electric field as shown in FIG. 2C. At the same time, the electron concentration at the source gradually increases. The breakdown voltage avalanche effect causes the holes to be swept across from the drain to the source and causes electron injection from the source to the drain. As can be seen in FIG. 2A, some of the holes are diverted into the gate 10 which is separated from the p-well only by a thin gate oxide 30. As mentioned above, the gate coupling effect can be adjusted by adjusting the voltage on the gate thereby allowing the triggering voltage to be further reduced by limiting the number of holes that are diverted into the gate. The snap back triggering characteristic of the NMOS device of FIGS. 1 and 2, is used to switch the device into a high conductivity state with avalanche injection at some critical level of drain-source breakdown.
The breakdown characteristics of the NMOS device described above are illustrated in FIG. 3 in which the drain current versus drain-source voltage characteristics are shown. As the drain-source voltage (Vds) increases, drain current (Id) remain substantially unchanged until the breakdown voltage (Vbr) 32 is reached. This causes rapid increase in Id. Eventually the hole concentration and electron concentration at the drain and source, respectively, is reversed, as defined by the triggering voltage (Vtr) 34. At this point, even with reduced Vds, the drain current continues to increase thus defining the snap back effect.
A drawback of these prior art devices, when used as ESD protection solutions, is that the gate oxide is too thin to provide reliable operation. One solution adopted is to split the gate voltage, thereby keeping the voltage below critical values. The present invention seeks to provide a more robust solution to the use of MOS devices used as ESD protection clamps.
According to the invention, there is provided an ESD protection clamp making use of a modified MOS device, and preferably making use of a modified NMOS snap back structure. The gate oxide is replaced by a composite-to-composite spacing in the form of a shallow trench isolation (STI) region which is used in conjunction with dynamic substrate control using a sub-circuit to adjust the substrate potential and thus reduce the triggering voltage. Without the dynamic substrate control, the modified NMOS structure would display high breakdown voltages due to the substantial spacing caused by the STI which would make the device unsuitable for ESD protection. By way of comparison, a conventional NMOS snap back structure making use of the polygate as a self-aligned mask which is separated from the p-well by a thin gate oxide, displays typical drain-source spacing of approximately 0.2 xcexcm for a 0.5 xcexcm gate. In contrast, a modified structure making use of STI would display an oxide isolation region between the drain and the source of approximately 0.35 xcexcm width.
The present invention therefore replaces the dynamic gate coupling effect of the prior art with a modified structure and the use of substrate coupling in order to reduce the breakdown and triggering voltages of the modified structure. The modified structure of the present invention has the advantage of avoiding gate oxide breakdown. It provides for better heat dissipation and reduces hot carrier degradation, an effect evident in NMOS devices over a long period of time. The effect of hot current degradation is that current drain-source voltage gradually increases due to degradation of the device.
Further according to the invention, there is provided a method of providing ESD protection comprising providing a modified MOS device in which the gate oxide has been eliminated and a STI region introduced to provide a composite-to-composite spacing, and increasing the substrate voltage to reduce the triggering voltage of the structure.
Still further according to the invention, there is provided a method of providing ESD protection comprising providing a modified MOS structure in which the gate oxide has been eliminated and a STI region introduced between the drain and the source of the structure, and injecting carriers into the substrate to reduce the breakdown voltage.
Further according to the invention, in a MOS device having a drain and a source separated by a STI region, triggering voltage is reduced by means of dynamic substrate control, which includes injecting carriers into the substrate or increasing the voltage of the substrate.